This invention relates to a DMOS device, and more particularly relates to a DMOS device having a trenched bus structure.
The diffused metal-oxide-semiconductor (DMOS) transistor, one of the important power transistors, is widely used in high-voltage systems such as power suppliers and power control devices. Among many reported power transistor structures, a trenched power transistor is a notable design. Some reports have suggested a trenched power transistor has better performance than a planar power transistor in both efficiency and density.
As shown in FIG. 1, a known trenched DMOS device and its gate bus are illustrated. A typical trenched transistor is illustrated on the left side of FIG. 1, comprising (1) a plurality of trenches 220 formed in a P substrate 210, (2) a gate oxide layer 230 in the device region, lining the surface of the trenches 220 and extending to cover the top surface of the neighboring P substrate (or body) 210, (3) a plurality of N+ source regions 250 encompassing the DMOS trenches and extending to the top surface of the P substrate 210, and (4) a plurality of P+ regions 251 formed between two adjacent N source regions 250. The DMOS trench 220 has a bottom penetrating through an area below the P substrate 210. The inner part of the DMOS trench is filled with a gate polysilicon 241 to form a gate for the power transistor. A first isolation layer 261 and a source metal contact layer 270 cover in sequence over the gate polysilicon 241 and the gate oxide layer 230 in the device region. The source metal contact layer 270 has connections with the N source regions 250 and the P+ regions 251.
A typical gate bus is shown on the right side of FIG. 1, comprising (1) a polysilicon bus 242 formed over the P substrate 210 covered by a bus gate oxide layer 232 and (2) a second isolation layer 262 overlying the polysilicon bus 242 and the adjacent bus gate oxide layer 232 in the neighborhood and having an opening to expose the top surface of the polysilicon bus 242. Meanwhile, a gate metal conductive line 271 is connected over the polysilicon bus 242.
According to the abovementioned known trenched DMOS transistor and its gate bus structure, as shown in FIGS. 2A and 2B, a lithographic process is used, after the deposition of the polysilicon layer 240, to form a photoresist 245 for defining a location of the polysilicon bus 242 in order to form the polysilicon bus 242. Then an etching process is performed. As shown in FIG. 3, during the etching process to form the polysilicon bus 242, the charges and etching solution accumulate easily at the interface A of sidewalls of the polysilicon bus 242 and the adjacent gate oxide layer 230. Therefore, the gate oxide layer 230 at the interface A often suffers a severe etching action, so as to form micro trenches 300. Due to the formation of the micro trenches 300, more charges accumulate between the polysilicon bus 242 and the P substrate 210. It results in electric field breakdown of the gate oxide layer 230 at the interface A and the increase of current leakage.
FIG. 6 illustrates a DMOS transistor and its bus structure described in U.S. Pat. No. 6,031,265. The bus is formed from a trenched structure instead of a conventional planar one. The bus trench 221 and the DMOS trench 220 are formed in the same etching. With the subsequent blanket deposition, the polysilicon layer 240 fills the DMOS trench 220 and the bus trench 221. Then, an etchback process is directly performed with the gate oxide layer 230 as an etching stop layer. Therefore, a gate polysilicon 241 and a polysilicon bus 242 are formed respectively in the DMOS trench 220 and the bus trench 221.
According to the abovementioned bus structure design, there is no need for an additional lithographic process to form the polysilicon bus 242. However, due to the easy accumulation of the etching solution and charges on the top surface of the polysilicon bus 242 during the etching process of forming the polysilicon bus 242, the micro trenches 300 are easily formed in the gate oxide layer 230 of the adjacent bus.